Treffer: A new parallel architecture for discrete Hartley transform.

The Discrete Hartley Transform (DHT) is now widely used in various important signal processing applications, such as image compression, scientific computing, and harmonics analysis, etc. To improve its computational efficiency, a parallel architecture is often desirable. However, reducing its arithmetic complexity remains a challenge in all existing parallel architectures. In this work, we propose a systematic decomposition method leveraging the Kronecker product and stride permutation, enabling DHT computation with a significantly reduced number of multipliers. For transform sizes of 8, 16, and 32 points, the proposed architecture requires only 2, 10, and 34 multipliers, respectively. Moreover, it reduces hardware resource utilisation by approximately 17% without compromising parallel processing efficiency. The introduction of pipelining also improves the computational speed by 29.6% to 69.7% as obtained through simulation on a Xilinx Kintex UltraScale Field Programmable Gate Array (FPGA) board. Thus, it ensures an optimal balance between hardware efficiency and computational speed. Experimental results so obtained validate its superior performance in terms of computational efficiency and hardware resource utilisation compared to existing architectures. [ABSTRACT FROM AUTHOR]