CHISTIAKOV, A. Yu. und ZAPLETINA, M. A., 2025. Backpass Trees on a Mixed Route Graph for Accelerated FPGA Routing. Russian Microelectronics. 15 Dezember 2025. Vol. 54, no. 7, p. 751-755. DOI 10.1134/S1063739725700106.
Elsevier - Harvard (with titles)Chistiakov, A.Y., Zapletina, M.A., 2025. Backpass Trees on a Mixed Route Graph for Accelerated FPGA Routing. Russian Microelectronics 54, 751-755. https://doi.org/10.1134/S1063739725700106
American Psychological Association 7th editionChistiakov, A. Y., & Zapletina, M. A. (2025). Backpass Trees on a Mixed Route Graph for Accelerated FPGA Routing. Russian Microelectronics, 54(7), 751-755. https://doi.org/10.1134/S1063739725700106
Springer - Basic (author-date)Chistiakov AY, Zapletina MA (2025) Backpass Trees on a Mixed Route Graph for Accelerated FPGA Routing.. Russian Microelectronics 54:751-755. https://doi.org/10.1134/S1063739725700106
Juristische Zitierweise (Stüber) (Deutsch)Chistiakov, A. Yu./ Zapletina, M. A., Backpass Trees on a Mixed Route Graph for Accelerated FPGA Routing., Russian Microelectronics 2025, 751-755.