*Result*: FPGA framework improvements for HPC applications

*In modern FPGA devices, place and route has become an increasingly difficult task due to an increase in resources and device complexity. This results in an exponential increase of implementation possibilities. Such a huge search space causes tools to have a hard time providing a good solution. This is even more challenging in chiplet-based devices due to their topology. In the same way, off-chip memory resources have grown both in size and number of modules. These resources are presented to the user as raw memory interfaces requiring the user to manage how accelerator kernels access off-chip memory to make effective use of the available bandwidth. Efficient usage of memory resources becomes a critical challenge as the more computational resources are added to a design the more pressure they impose on the memory subsystem. This work proposes new features to the OmpSs@FPGA programming model in order to mitigate these issues in a transparent way for programmers. ; This work is supported by the TEXTAROSSA project G.A. n.956831, as part of the EuroHPC initiative, by the Spanish Government (Grants PCI2021-121964-TEXTAROSSA, PID2019-107255GB-C21 MCIN/AEI/10.13039/501100011033, and CEX2021-001148- S), and by Generalitat de Catalunya (2021 SGR 01007). ; Peer Reviewed ; Postprint (author's final draft)*