• A Systolic Array Architecture...

Treffer: A Systolic Array Architecture for Fast Decoding of One-Point AG Codes and Scheduling of Parallel Processing on It

Title:
A Systolic Array Architecture for Fast Decoding of One-Point AG Codes and Scheduling of Parallel Processing on It
Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
Authors:
Sakata, S., Kurihara, M.
Source:
LECTURE NOTES IN COMPUTER SCIENCE. (1719):302-313
Availability:
http://explore.bl.uk/primo_library/libweb/action/display.do?tabs=detailsTab&gathStatTab=true&ct=display&fn=search&doc=ETOCRN070293936&indx=1&recIds=ETOCRN070293936
Database:
British Library Document Supply Centre Inside Serials & Conference Proceedings